PCIe Timing Interface

Document #:

LIGO-E2000328-x0

Document type:

E - Engineering documents

Abstract:

The PCIe based timing interface integrates with the DAQ system and provides the 2^N Hz clocks needed for the Advanced LIGO converters. The timing signal is received by a standard 100base-FX SFP module. It uses a 37-pin D-sub connector to interface with the new IO backplane. It has the ability to provide individual clock signals to each converter that can be started in synchronization with the next 1 second mark. To support the DAQ software, GPS time stamps can be read out through the PCIe bus. Additional expansion options are possible to support a master oscillator with GPS interface as well as a number of timing fan-out ports.

It replaces several boards in the old design: the chassis timing interface with the DuoTone daughter boards, the IRIG-B timing PCIe board, and the binary IO board which was used to interface the old backplane.

Files in Document:

None

Topics:

• Data Acquisition System

Authors:

• Marc Pirello
• Daniel Sigg

Keywords:

Timing PCIe

Notes and Changes:

Wiki: https://awiki.ligo-wa.caltech.edu/wiki/PCIeTimingInterface
Adnaco Info:
http://www.adnaco.com/doc/Adnaco-Gen2-UG.pdf
https://www.adnaco.com/doc/Adnaco-R1BP1B-DS.pdf

Related Documents:

• LIGO-T1900639: PCIe Implementation of Timing Interface System
• LIGO-D2000329: PCIe Timing Interface Board
• LIGO-D2000331: PCIe Timing Interface Daughter Board Template
• LIGO-D2000297: IO Interface Backplane (LVDS)
• LIGO-D2000301: Master Clock Expansion Option
• LIGO-D2000302: Fanout Expansion Option
• LIGO-T2000406: Software Interface to the PCIe Timing Board
• LIGO-E2000337: PCIe Timing Interface Software Release
• LIGO-E2300446: PCIe Timing Interface Software Release (XC7A50T)
• LIGO-T2100299: IO Interface Backplane Test Procedures
• LIGO-D2100184: Backplane Test Adapter

Referenced by:

• LIGO-E090003-v1: Timing System Document Map Advanced LIGO
• LIGO-D1900002-v1: aLIGO, DAS, IO EXPANSION CHASSIS, MECHANICAL ASSY, W SPACERS