LIGO Document E2000328-x0
- The PCIe based timing interface integrates with the DAQ system and provides the 2^N Hz clocks needed for the Advanced LIGO converters. The timing signal is received by a standard 100base-FX SFP module. It uses a 37-pin D-sub connector to interface with the new IO backplane. It has the ability to provide individual clock signals to each converter that can be started in synchronization with the next 1 second mark. To support the DAQ software, GPS time stamps can be read out through the PCIe bus. Additional expansion options are possible to support a master oscillator with GPS interface as well as a number of timing fan-out ports.
It replaces several boards in the old design: the chassis timing interface with the DuoTone daughter boards, the IRIG-B timing PCIe board, and the binary IO board which was used to interface the old backplane.
DCC Version 3.4.1, contact
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