PCIe Timing Interface Daughter Board Template
- Document #:
- LIGO-D2000331-v1
- Document type:
- D - Drawings
Other Versions:
- Abstract:
- A simple daughter board for the PCIe timing interface. It routes 58 of the 64 available LVDS lines to a rear DB37 and a front 80-pin connector.
- Files in Document:
-
- D2000331-v1.pdf (file is not accessible)
- Other Files:
- D2000331-v1.zip (file is not accessible)
- Daugher Card Image Attached.JPG (file is not accessible)
- Daugher Card Image Rear.JPG (file is not accessible)
- Daugher Card Image.JPG (file is not accessible)
- ICS/JIRA Record:
-
- ICS_LINK
- Topics:
- Authors:
- Referenced by:
- LIGO-E2000328: PCIe Timing Interface