PCIe Timing Interface Board

Document #:

LIGO-D2000329-v2

Document type:

D - Drawings

Abstract:

Schematics and PCB of the PCIe timing interface.

Files in Document:

• D2000329v2.pdf (file is not accessible)

Other Files:

• ChassisTimingInterface (3-7-2023).zip (file is not accessible)
• ChassisTimingInterface(6-8-2021).xls (file is not accessible)
• ChassisTimingInterface(9-29-2023).xls (file is not accessible)

ICS/JIRA Record:

• ICS_LINK

Topics:

• Data Acquisition System

Authors:

• Marc Pirello

Keywords:

PCIE Timing Interface IO Chassis

Notes and Changes:

Minor changes to the PCB, added RS485 transciever, more clock options, and test points.
First Run - L1 changed to 33nH, C23 removed, R5 reduced to 5k.
R94 is changed to adjust range of the VCXO. 22k for Bomar, 7.15k for Vectron.

Related Documents:

Referenced by:

• LIGO-E2000328: PCIe Timing Interface