LIGO Document D1400301-v15
- A block diagram showing the proposed design topology for a chassis that allows transition to a low voltage drive mode for noise reduction in the ESD drive chain on the ETMs. This chassis also provides a 40vp-p drive capability. Scattered features existing in the initial ESD subsystem installation (bias voltage low pass filter, 10kohm series resistors) are consolidated into this design.
- V15 – Changed the DAC filtration block from Pole/Zero 2.2/50Hz to 2.2/15Hz per ECR E1800233. Added details associated with old ECR E1600230 for PI Correction while in HV mode. Per E1500443, changed the monitoring amplifier Low Pass corner frequency from 43.5kHz to 43.5Hz
DCC Version 3.4.2, contact
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