ETM and ITM ESD Low Voltage Driver Block Diagrams

Document #:

LIGO-D1400301-v15

Document type:

D - Drawings

Abstract:

A block diagram showing the proposed design topology for a chassis that allows transition to a low voltage drive mode for noise reduction in the ESD drive chain on the ETMs. This chassis also provides a 40vp-p drive capability. Scattered features existing in the initial ESD subsystem installation (bias voltage low pass filter, 10kohm series resistors) are consolidated into this design.

Files in Document:

• PDF Version (NewESD_v15.pdf, file is not accessible)

Other Files:

• Visio Version (NewESD_v15.vsd, file is not accessible)

ICS/JIRA Record:

• ICS_LINK

Topics:

• Sensing and Control

Authors:

• Rich Abbott
• Peter Fritschel
• Carl Adams
• Dean Schaetzl

Keywords:

ESD

Notes and Changes:

V15 – Changed the DAC filtration block from Pole/Zero 2.2/50Hz to 2.2/15Hz per ECR E1800233. Added details associated with old ECR E1600230 for PI Correction while in HV mode. Per E1500443, changed the monitoring amplifier Low Pass corner frequency from 43.5kHz to 43.5Hz

Related Documents:

• LIGO-D1600077: ITM PI AI Chassis
• LIGO-D1500016: ETM Low Voltage Low Noise Electro-Static Driver Main Board

Referenced by:

• LIGO-E1600101: PI damping, Electronics
• LIGO-E1500015: ETM and ITM Low Voltage Electro-Static Driver Documentation