ESD Low Voltage Driver Block Diagram
- Document #:
- LIGO-D1400301-v11
- Document type:
- D - Drawings
Other Versions:
| LIGO-D1400301-v15
04 Oct 2018, 13:23 |
| LIGO-D1400301-v14
12 Sep 2016, 08:19 |
| LIGO-D1400301-v13
10 Mar 2016, 16:58 |
| LIGO-D1400301-v12
17 Feb 2016, 13:23 |
| LIGO-D1400301-v10
18 Mar 2015, 17:18 |
| LIGO-D1400301-v9
21 Jan 2015, 16:14 |
- Abstract:
- A block diagram showing the proposed design topology for a chassis that allows transition to a low voltage drive mode for noise reduction in the ESD drive chain on the ETMs. This chassis also provides a 40vp-p drive capability. Scattered features existing in the initial ESD subsystem installation (bias voltage low pass filter, 10kohm series resistors) are consolidated into this design.
- Files in Document:
-
- PDF Version (NewESD_v11.pdf, file is not accessible)
- Other Files:
- Visio Version (NewESD_v11.vsd, file is not accessible)
- ICS/JIRA Record:
-
- ICS_LINK
- Topics:
- Authors:
- Keywords:
- ESD
- Notes and Changes:
- Version 11 Notes:
Updated TVS to a diode clamp. Added DAC noise model equation. Updated 200 ohm series current limiting resistor. Added Test Port and binary readbacks.
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