ESD Low Voltage Driver Block Diagram

Document #:

LIGO-D1400301-v12

Document type:

D - Drawings

Abstract:

A block diagram showing the proposed design topology for a chassis that allows transition to a low voltage drive mode for noise reduction in the ESD drive chain on the ETMs. This chassis also provides a 40vp-p drive capability. Scattered features existing in the initial ESD subsystem installation (bias voltage low pass filter, 10kohm series resistors) are consolidated into this design.

Files in Document:

• PDF Version (NewESD_v12.pdf, file is not accessible)

Other Files:

• Visio Version (NewESD_v12.vsd, file is not accessible)

ICS/JIRA Record:

• ICS_LINK

Topics:

• Sensing and Control

Authors:

• Rich Abbott
• Peter Fritschel
• Carl Adams

Keywords:

ESD

Notes and Changes:

Version 12:
Updated the monitoring chain LPF from 1kHz to 4.244kHz as implemented by D1500443 (1kHz was a calculation error). Added new whitening amplifier board block element (D1500389) that was inserted in the monitoring chain.

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