Timing Slave

Document #:

LIGO-D070071-x0

Document type:

D - Drawings

Abstract:

Timing Slave FPGA board

Files in Document:

• D070071-B.pdf (file is not accessible)

Other Files:

• D070071-A.pdf (file is not accessible)
• D070071-A.zip (file is not accessible)
• D070071-B.zip (file is not accessible)

ICS/JIRA Record:

• ICS_LINK

Topics:

• Document Migration from the old DCC
• Data Acquisition System

Authors:

• Daniel Sigg

Keywords:

Timing Slave FPGA board

Notes and Changes:

Rev D070071-B-D:
- Full document number: LIGO-D070071-B-D
- Author(s): Daniel Sigg
- Document date: 2008-04-18
- Document received date: 2008-05-06
- Document entry date: 2008-05-06

Rev D070071-A-D:
- Full document number: LIGO-D070071-A-D
- Author(s): Daniel Sigg
- Document date: 2007-03-16
- Document received date: 2007-03-19
- Document entry date: 2007-03-19

Referenced by:

• LIGO-E0900016-v1: Integration Plan Slave Module Advanced LIGO
• LIGO-D0900301-v1: Timing IRIG-B
• LIGO-E090001-v1: Chassis Integration Plan Clock, Gate, and DuoTone Signal Interface Advanced LIGO
• LIGO-E090003-v1: Timing System Document Map Advanced LIGO
• LIGO-D1001715-v3: aLIGO, DAS, IO EXPANSION CHASSIS, MECHANICAL ASSY