Altium

Design Rule Verification Report

Date: 3/1/2021
Time: 9:09:57 AM
Elapsed Time: 00:00:04
Filename: C:\Users\Daniel\Documents\Protel\marc.pirello\Solutions\ISC - PCIe Duotone\New Backplane\NewBackplane.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=5mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=5mil) (Max=50mil) (Preferred=6mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=15mil) (Conductor Width=15mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=5mil) (All) 0
Hole Size Constraint (Min=10mil) (Max=200mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All) 0
Silk To Solder Mask (Clearance=1mil) (IsPad),(All) 0
Silk to Silk (Clearance=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Room BP1 (Bounding Region = (13569.999mil, 10799.999mil, 15169.999mil, 15999.999mil) (InComponentClass('BP1')) 0
Room BP2 (Bounding Region = (11969.999mil, 10799.999mil, 13569.999mil, 15999.999mil) (InComponentClass('BP2')) 0
Room BP3 (Bounding Region = (10369.999mil, 10799.999mil, 11969.999mil, 15999.999mil) (InComponentClass('BP3')) 0
Room BP5 (Bounding Region = (7169.999mil, 10799.999mil, 8769.999mil, 15999.999mil) (InComponentClass('BP5')) 0
Room BP4 (Bounding Region = (8769.999mil, 10799.999mil, 10369.999mil, 15999.999mil) (InComponentClass('BP4')) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 0