Design Rule Verification Report
Date:
3/6/2019
Time:
12:15:34 PM
Elapsed Time:
00:00:01
Filename:
C:\Users\daniel.sigg\Documents\Protel\RF\VCO\VCORelay.PcbDoc
Warnings:
0
Rule Violations:
0
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=10mil) (All),(All)
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Un-Routed Net Constraint ( (All) )
0
Width Constraint (Min=12mil) (Max=100mil) (Preferred=12mil) (All)
0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
0
Hole Size Constraint (Min=12mil) (Max=150mil) (All)
0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
0
Total
0
