Altiumcustomize

Design Rule Verification Report

Date : 9/27/2013
Time : 1:49:04 PM
Elapsed Time : 00:00:05
Filename : D:\Users\daniel\Protel\CommonMode\SummingNode\CMSum.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Vias Under SMD Constraint (Allowed=Not Allowed) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=12mil) (Air Gap=12mil) (Entries=4) (All) 0
Clearance Constraint (Gap=10mil) (All),(All) 0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=12mil) (All) 0
Hole Size Constraint (Min=18mil) (Max=150mil) (All) 0
Un-Routed Net Constraint ( (All) ) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All) 0
Silk To Solder Mask (Clearance=2mil) (IsPad AND NOT (HasFootprint('CA-ALL3') OR HasFootprint('CA-ALL6') OR HasFootprint('CA-ALL8'))),(All) 0
Silk to Silk (Clearance=4mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Minimum Annular Ring (Minimum=8mil) (All) 0
Total 0