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Design Rule Verification Report

Date : 9/8/2008
Time : 11:35:21 AM
Elapsed Time : 00:00:00
Filename : C:\User\Daniel\Protel\Timing\TimingSlave\TestDaughter\TestDaughter.PcbDoc
Warnings : 0
Rule Violations : 0

Summary

Warnings Count
Total 0

Rule Violations Count
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Broken-Net Constraint ( (All) ) 0
Clearance Constraint (Gap=10mil) (All),(All) 0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=10mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Hole Size Constraint (Min=8mil) (Max=250mil) (All) 0
Total 0