Design Rule Verification Report
Date:
1/7/2020
Time:
9:44:55 AM
Elapsed Time:
00:00:00
Filename:
C:\Dean\A+\D1900197 AI_Chassis\D070101-v2 16bit_DAC_AI_Rear_Interface_PCB\v3\D070101-v3 16bit_DAC_AI_Rear_PCB.PcbDoc
Warnings:
0
Rule Violations:
0
Summary
Warnings
Count
Total
0
Rule Violations
Count
Clearance Constraint (Gap=10mil) (All),(All)
0
Short-Circuit Constraint (Allowed=No) (All),(All)
0
Un-Routed Net Constraint ( (All) )
0
Width Constraint (Min=10mil) (Max=100mil) (Preferred=10mil) (All)
0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
0
Hole Size Constraint (Min=1mil) (Max=200mil) (All)
0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
0
Total
0